A Generic Instruction Set Architecture Model in Event-B for Early Design Space Exploration

The Instruction Set Architecture (ISA) is the part of a computer’s architecture visible to programmers. It specifies basic data types, instructions, internal storage, addressing modes, memory architecture and interrupt/exception handling of a computer. Design decisions at ISA level not only determine the computer’s functional behaviour, but also influence non-functional properties such as performance, energy efficiency and even design effort. To allow computer architects to make informed decisions it is important that they can explore the impact of different design options at an early stage. For this, a generic modeling framework for ISAs is needed as a foundation. This paper introduces a generic ISA model in Event-B. The model is refined over four main abstraction levels in a series of horizontal and vertical refinement steps. At each level, choice points are built into the model, permitting exploration of different design options. The model was evaluated on a performance-optimized cryptographic processor. Design Space Exploration, Generic ISA Model, Event-B